| 摘要 |
<p>PURPOSE:To reduce the power consumption by providing a 2nd tri-state gate controlled by an output signal of a detection circuit to a latch circuit. CONSTITUTION:A signal through an internal bus 60 is inputted to buffer gates 50, 51 and an inverter 31, an output of the inverter 31 is inputted to a PMOS transistor(TR) 412 and an NMOS 412 of a clocked inverter 40 and an output of the clocked inverter 40 is outputted to an internal bus 60. Then an output of 3-state gates 10-12 whose output state is controlled by control signals 20-22 respectively is outputted to the internal bus 60, and the control signals 20-22 are inputted to a NOR gate 70, its output is inputted to an NMOS TR 422 in the clocked inverter 40 and an inverter 30 and an output of the inverter 30 is inputted to a PMOS TR 411 of the clocked inverter 40.</p> |
