| 摘要 |
PURPOSE: To provide a phase locked loop which generates an output clock signal. CONSTITUTION: A phase locked loop 22 is provided with a phase/frequency circuit 12, a charge pump circuit 14, a voltage-controlled oscillator 16, and first and second frequency-dividing circuits 23 and 18. The circuit 12 generates a first control signal in response to a prescribed phasic relation between first and second clock signals and the circuit 14 generates a voltage in response to the first control signal. The oscillator 16 generates a third clock signal in response to the voltage and the circuits 24 and 18 respectively divide the frequency of the third clock cycle by first and second ratios. The first ratio is controlled by a second control signal. The outputs of the circuits 24 and 18 respectively generate an output clock signal and the first clock signal. The VCO band width condition of the phase locked loop 22 for a given operating environment is not strict and the loop 22 can make phase locking in a short time when the ratio between input and output clock frequencies is changed. |
