发明名称 PLL CIRCUIT
摘要 PURPOSE:To attain low voltage drive without the need for using an active filter by changing a range of an output voltage of a passive filter provided to a PLL loop in the vicinity of a potential of a power supply line. CONSTITUTION:A charge pump circuit 2 is made up of a CMOS push-pull circuit in which a source of a FET transistor(TR) 1 connects to a upstream of a power supply line VCC and a source of a downstream side FET TR 2 connects to ground. Then a no active filter but a passive filter (lag/lead filter) 3 is adopted for a filter of a PLL loop of a voltage controlled oscillator circuit (VCO) 11, and an upstream side TR 1 connects directly to the power supply line VCC and the push-pull output circuit receives the comparison result signal from the phase comparator circuit 24 and is provided as an output to the lag lead filter 3. Thus, the range of the output voltage of the lag lead filter 3 is changed in the vicinity of a potential of the power supply line VCC.
申请公布号 JPH07154251(A) 申请公布日期 1995.06.16
申请号 JP19930329653 申请日期 1993.12.01
申请人 ROHM CO LTD 发明人 SUZUKI TAMOTSU;SHIMADA GIICHI
分类号 H03L7/18;H03L7/093 主分类号 H03L7/18
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