SUPERSCALAR PIPELINE-TYPE PROCESSOR WITH REINFORCED PIPE CONTROL AND REGISTER CONVERSION FUNCTION

摘要

PURPOSE: To accelerate the speed of processing instructions by performing control so as not to make a first instruction in a present stage be delayed by the data dependency as long as it is not required to solve the data dependency in the second instruction of a different pipeline for appropriately processing the first instruction in the present stage of one pipeline. CONSTITUTION: In this super scalar pipeline type processor provided with a plurality of instruction pipelines provided with a plurality of processing stages, a pipe control means detects the dependency among the instructions in the pipelines and controls the flow of the instructions passed through the stages of the pipelines. That is, the respective stages (n-1)-(n+1) among the pipeline stages are provided with peculiar input STALL from the pipe control means and output DELAY. The DELAY is enabled in the case of requiring at least one more clock for completing the instruction provided in the stage and the STALL is enabled by the control means when the stage can not transfer the instruction to a consequent stage.