| 摘要 |
PURPOSE:To decrease the number of pieces of register control signals, to reduce the register area, end also to minimize the read/write delay of data by connecting the output terminal of a general-purpose register set and the input terminal of an output register set to an exclusive write bus. CONSTITUTION:The output terminals BX, BY, CX and CY of unit registers 111-114 included in a general-purpose register set 150 are connected to an exclusive write bus 181BX, etc. Meanwhile the input terminals BXI BYI, CXI end CYI of unit output registers 161-164 included in an output register set 160 are connected to the bus 181BX, etc. Then the output terminals BOUT and COUT of each unit output register are connected to an internal write bus included in a CPU. in such a constitution, the load capacity of the data output means of each of registers 111-114 is reduced to the bus. Therefore the sizes of transistors constructing the output means of registers 111-114 can be reduced, and just two control signals suffice for transmission of data. |
