Memory monitoring circuit for detecting unauthorized memory access.

摘要

The memory security circuit detects when a memory unit (NVM3) has been accessed independently of an address instruction (AS) of a programmable microprocessor (13). The microprocessor (13) is programmed to provide a unique address signal (AS) for write enabling a discrete memory unit (NVM3). The memory unit has a write enable pin (P5) and chip select pin (P6) which when enabled in combination permits writing into the memory unit (NVM3). The address decoder (28) receives the unique address instruction (AS) and causes a write enable signal and a chip select signal to be generated for that memory unit (NVM3). The write enable signal and chip select signal are to be received, respectively, by the write enable pin (P5) and the chip select pin (P6) of the memory unit (NVM3). The memory security circuit monitors the write enable pin (P5) and the chip select pin (P6) of the memory unit (NVM3) and generates a first output signal when the memory unit has been properly addressed. A second output signal (INTERRUPT 2) is generated when the memory unit (NVM3) has not been addressed by the address decoder (28) and the write enable and the chip select signals are present at the memory unit (NVM3). <IMAGE>