Method and device for detecting and controlling an array source signal discharge for a memory erase operation

摘要

An array source signal discharge controller device (10) includes a pulse converter circuit (12) that receives an erase pulse signal (ERPULSE). The pulse converter circuit (12) converts the erase pulse signal (ERPULSE) into a pulse control signal (ERPCL) that is subsequently translated into a higher voltage level bias signal (ECL-). The higher voltage level bias signal (ECL-) drives array source signal generator circuits (16) that produce array source signals (AS) to erase particular array subsections of memory as determined by a selection circuit (17). The array source signal generator circuits (16) also generate array source command signals (ASCOM-) to indicate a discharging status of all array source signals (AS). An erase completion detector circuit (18) monitors the array source command signals (ASCOM-) and generates an array source detect signal (ASDET) to indicate completion of array source signal (AS) discharging. The pulse converter circuit (12) receives the array source detect signal (ASDET) and generates an erase completion signal (ERCTR) and a pulldown control signal ERCTR- to control final discharge of the array source signals (AS) and indicate that normal memory access may resume. The pulse converter circuit (12) also generates a pulldown signal (ERD-) that controls discharge of the array source signals (AS) by preventing current surges from appearing on the array source signals (AS) during discharge.