发明名称 Filtering device for use in a phase locked loop controller
摘要 A phase lock loop (PLL) frequency synthesizer is used in a radiotelephone to provide a reference frequency to a transmitter or a receiver. This particular PLL frequency synthesizer has a wide bandwidth control loop having a high current charge pump (417) and a narrow bandwidth control loop having a low current charge pump (411). A deadzone circuit (413) is used at an output of a phase detector (405) to control the application of an error signal to the high current charge pump (417). Additionally, the PLL frequency synthesizer utilizes a loop filter (419). The loop filter (419) receives two correction signals (409', 415') and provides a single control signal for the VCO (voltage controlled oscillator) (423). The loop filter contains two time constants formed from resistive and capacitive elements. The two time constants control the bandwidth of the two control loops.
申请公布号 US5424689(A) 申请公布日期 1995.06.13
申请号 US19930172000 申请日期 1993.12.22
申请人 MOTOROLA, INC. 发明人 GILLIG, STEVEN F.;HIETALA, ALEXANDER W.
分类号 H03L7/089;H03L7/107;(IPC1-7):H03L7/093 主分类号 H03L7/089
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