| 摘要 |
An adjustable digital synthesizer has frequency increments of a selected step size. The adjustable digital synthesizer includes a digital accumulator having N stages. The digital accumulator counts at a predetermined clock frequency such that, in response to each clock, the accumulator increments the step size determined by the digital input. The accumulator counts to 2Nth state and wraps around in response to an overflow. An adder, responsive to the overflow, adds an offset to the accumulator, the offset being a function of the difference between 2Nth times the minimum step size and the desired clock frequency.
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