发明名称 Mechanism for reducing timing jitter in clock recovery scheme for blind acquisition of full duplex signals
摘要 Timing jitter in the clock recovery loop of a 'blind' signal acquisition receiver employing a square law detector in a phase lock loop signal flow path is substantially reduced by adaptively adjusting the parameters of the loop's pre-filter, so as to compensate for conjugate antisymmetric components in the spectrum of the monitored signal of interest. The signal timing recovery signal processing mechanism includes a filter parameter adjustment operator which controllably sets the weighting parameters of a baseband prefilter, so that the filtered signal does not possess conjugate antisymmetry about the Nyquist frequency and the spectrum of the filtered signal is essentially conjugate symmetric.
申请公布号 US5425060(A) 申请公布日期 1995.06.13
申请号 US19930008425 申请日期 1993.01.25
申请人 HARRIS CORPORATION 发明人 ROBERTS, RICHARD D.;WEBSTER, MARK A.
分类号 H04L7/027;(IPC1-7):H04L7/00;H04L25/36;H04L25/40 主分类号 H04L7/027
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