发明名称 |
Method and apparatus for bit stream synchronization |
摘要 |
A data processing system (10) is described which comprises an integrated decoder circuit (12) comprising an input buffer (14) and an error signal generator circuit ( 18 ) . The error signal generator circuit ( 18 ) generates a pulse width modulated error signal output to a clock processing circuit (20). The clock processing circuit (20) may comprise a low pass filter (24) and a variable oscillator (26). The clock processing circuit (20) supplies a clock signal to a digital-to-analog converter (16). The digital-to-analog converter (16) uses the clock signal to correctly track the bit rate for the encoded bit stream received by decoder system (12).
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申请公布号 |
US5425061(A) |
申请公布日期 |
1995.06.13 |
申请号 |
US19930071744 |
申请日期 |
1993.06.07 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
LACZKO, SR., FRANK L.;WALKER, KAREN L. |
分类号 |
H03M1/66;H04L7/08;H04L25/02;H04L25/05;H04N7/52;H04N7/62;(IPC1-7):H04L7/00;H04L23/00;H04J3/22 |
主分类号 |
H03M1/66 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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