摘要 |
The vector processor has a memory unit (101,109) for taking a text vector (102) containing a text signal sequence, a key word vector (144,145,146) of a type or form vector (103) containing the key word sign sequence having elements assigned to text signs or symbols and indicating whether the text signs appear in the key word vector, and a result vector (104). There is also a unit (152) for reading out the elements of the text vector (102). A unit (116) reads out those elements of the form vector (103) corresponding to the text signs. Control logic (111) establishes in the text sign sequence a candidate sign sequence appearing also in the key word vector. A memory (151) for this sequence, writes it into the result sequence and a processing unit (CPU, 118) determines whether this sequence agrees with the key word sign sequence. |
申请人 |
HITACHI, LTD., TOKIO/TOKYO, JP |
发明人 |
KOJIMA, KEIJI, KODAIRA, TOKIO/TOKYO, JP;MISHINA, YUSUKE, KUNITACHI, TOKIO/TOKYO, JP |