| 摘要 |
PURPOSE:To prevent a malfunction or the discontinuation of actuation owing to the reduction of the logic amplitude produced at a high frequency band, by adding a peaking circuit into a circuit connected in parallel to a feedback loop for a dynamic frequency divider provided with an inverter, a buffer amplifier and a transmitting gate which form the feedback loop. CONSTITUTION:A buffer amplifier 3 for extraction of output is connected in parallel to a feedback loop, and peaking ciricuits 13 and 14 are added at front and back sides of the amplifier 3 respectively. Furthermore peaking circuits 11 and 12 are added to input terminals 6 and 7 of transmitring gates 4 and 5 respectively. The delay time is generally increased with addition of peaking circuits and the circuit cut-off frequdncy is increased. Thus the peaking circuit is added at an area excepting the feedback loop to obtain the gain of a high frequency band. While no peaking circuit is used within a feedback loop where the increase of the delay time causes directly the reduction of the frequency dividing speed. Thus it is possible to increase the input sensitivity at a high frequency band with no reduction of the dividing speed. |
