发明名称 |
EQUIPMENT AND METHOD FOR DISTRIBUTING CLOCK TO CIRCUIT CONSTITUTING ELEMENT OF INTEGRATED CIRCUIT |
摘要 |
PURPOSE: To supply synchronous clock signals to the entire components of an integrated circuit with minimum signal skewness and distortion by uniformly arranging a plurality of global clock driver means for generating the synchronous clock signals along the periphery of the integrated circuit. CONSTITUTION: Global clock drivers 30 are arranged along the left and right ends of a microprocessor 200 and the respective global area drivers 30 send clock signals into the center part of the microprocessor 200 by a feed line 31. A common driver 301 supplies the clock signals through a common supply line 303 and common networks 340-344 to intermediate clock drivers 310-314. The intermediate drivers 310-314 are connected through intermediate networks 361-365 to the global area drivers 30. The respective lines of the common networks 340-344 are provided with similar RC values and thus, matching is performed relating to the resistance and capacitance values so as to be provided with the matched skewness. |
申请公布号 |
JPH07146733(A) |
申请公布日期 |
1995.06.06 |
申请号 |
JP19940155529 |
申请日期 |
1994.06.15 |
申请人 |
INTEL CORP |
发明人 |
KEN ERU UON;KEIRI JIEI FUITSUTSUPATORITSUKU;JIEFURII II SUMISU |
分类号 |
G06F1/10;G06F1/32;H01L21/82;H01L21/822;H01L27/04;H03K5/15;(IPC1-7):G06F1/10 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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