发明名称 PLL CIRCUIT
摘要 PURPOSE:To lock a reference signal having a wide range of frequencies to synchronization in an excellent way. CONSTITUTION:A PC 12 compares a phase difference between a reference signal (a) and a comparison signal (b) from a 1/N counter 16, gives an output signal in response to the phase difference to an integration circuit 18, from which a control signal (c) is obtained. The control signal (c) is given to a VCO 20 and a comparator 38. The comparator 38 compares the control signal (c) with a reference voltage (e) from a reference signal generating circuit 40 and a comparison signal depending on the relation of quantity is given to an integration circuit 42, from which a control voltage (f) is obtained and it is given to a varactor diode 46. The varactor diode 46 uses the control voltage (f) to control the F-V characteristic of the VCO 20 till the control voltage (c) is equal to the reference signal (e). The control voltage (c) given to the VCO 20 is set to an optimum value at all times so long as the reference signal (a) having a frequency within a predetermined range is given to the PC 12.
申请公布号 JPH07147538(A) 申请公布日期 1995.06.06
申请号 JP19930291873 申请日期 1993.11.22
申请人 SANYO ELECTRIC CO LTD 发明人 NAKAYAMA TAKESHI
分类号 H03L7/093;H03L7/10 主分类号 H03L7/093
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