SEMICONDUCTOR MEMORY DEVICE

摘要

PURPOSE:To provide a semiconductor memory device in which a constituent is arranged so as to comprise a simplified cache system with high hit ratio. CONSTITUTION:A data register 10 which comprises cache memory is arranged between the one terminal of a pair of bit lines in a memory cell array 5 which comprises main memory and an I/O bus 110. The data register 10 stores information read out in block unit from the memory cell array 5 in block unit. Furthermore, a cache string decoder 13 is arranged at a side opposite to the data register 10 for the I/O bus 110. The cache string decoder 13 controls the energizing/de-energizing state of an I/O switch 11 to transfer storage information in the data register 10 to the I/O bus 110 selectively.