发明名称 Method of erasing information in memory cells
摘要 A method of this invention is applied to a nonvolatile memory device composed of first memory cells connected to one of a first word-line pair and second memory cells connected to the other of the first word-line pair, and a single source shared by the first memory cells and the second memory cells. First, a positive potential of, for example, 5 V is applied to the source, a negative potential of, for example, -10 V is applied to the one of the word-line pair, and the ground potential to the other of the word-line pair. This permits electrons to move from the floating gate of the first memory cells into the source, with the result that the erasing of information is achieved. Next, the positive potential is applied to the source, the negative potential is applied to the other of the word-line pair, and the ground potential to the one of the word-line pair. This permits electrons to move from the floating gates of the second memory cells into the source, with the result that the erasing of information is achieved.
申请公布号 US5422843(A) 申请公布日期 1995.06.06
申请号 US19930123476 申请日期 1993.09.20
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 YAMADA, SEIJI
分类号 G11C17/00;G11C16/02;G11C16/04;G11C16/16;H01L21/8247;H01L27/115;(IPC1-7):G11C11/40 主分类号 G11C17/00
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