发明名称 DYNAMIC CLOCK SWITCHING CIRCUIT
摘要 PURPOSE: To enable a dynamic clock switching circuit to accept any type of carrier detecting systems by incorporating a means which switches a clock to an unused clock signal after a prescribed delay based on a carrier detecting signal in the circuit. CONSTITUTION: When an external clock circuit block 12 detects a carrier detecting signal 23, the external clock block 12 generates a control signal on a line 32 after an appropriate prescribed delay, outputs an external clock signal 19 as an output signal 50 to an external circuit through a path gate 40 and a latch 44. When the carrier detecting signal 23 does not exist, an internal clock circuit block 14 energizes the path gate 42 so that the external circuit may use an internal clock signal 21 by supplying a control signal onto a line 30a. A feedback line 30b is used for invalid signals and, when no external clock signal exists, clears the data in the delay block of an external clock block delay line and prevents the phase shift of an external clock when the clock is restarted.
申请公布号 JPH07147573(A) 申请公布日期 1995.06.06
申请号 JP19940098769 申请日期 1994.05.12
申请人 TEXAS INSTR INC <TI> 发明人 ANDORE SHIYUTSUIPANETSUKU
分类号 G06F1/08;H04L7/00;H04L7/04;H04Q11/04 主分类号 G06F1/08
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