| 摘要 |
<p>PURPOSE:To fix delay time from the clock buffer of an initial stage to respective flip-flop circuits without undergoing the restriction of the layout arrangement of elements. CONSTITUTION:A clock path for which the delay time from a master clock buffer 11 is the longest is defined as a reference path and delay circuits 51-55 provided with the respectively prescribed delay time are arranged in the preceding stage of the flip-flop circuits 41-45 so as to let the delay time from the master clock buffer 11 to the respective flip-flop circuits 41-46 be equal to the reference path.</p> |
