| 摘要 |
PURPOSE:To prevent deterioration in modulation accuracy due to deviation in a phase balance and production of carrier leakage. CONSTITUTION:A clock generator 11 generates a clock signal having a frequency 4fc being four times of a modulation carrier frequency fc and the generated clock signal is inputted to a 2-bit Gray code generator 12, from which 2-bit Gray codes G0, G1 are generated. The generated 2-bit Gray codes G0, G1 are respectively inputted to polarity inversion circuits 13, 14. An in-phase component I of the quadrature modulation signal is inputted to the polarity inversion circuit 13 and the polarity is inverted by a polarity of the Gray code G0 and a quadrature component Q of the quadrature modulation signal is inputted to the polarity inversion circuit 14 and the polarity is inverted by a polarity of the Gray code G1. The I and Q data whose polarity is inverted are added by an adder 15 and the sum is converted into an analog signal at a D/A converter 16 and the signal is outputted through a band pass filter 17. |
