Auxiliary control signal decode using high performance address lines

摘要

An apparatus that develops the M16* control signal, which indicates a 16 bit memory device is responding, from the latched address LA<> lines to provide a faster response time than if it were decoded from the SA<> address lines. Decode values for specific 8 kbyte blocks in a 128 kbyte address range are stored. The particular value for an 8 kbyte block is multiplexed and provided to the M16* line based on the decode of the LA address lines.