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发明名称
METODO E SISTEMA PER LA RIDUZIONE DEL JITTER DI UNA STRUTTURA A PLL (PHASE LOKED LOOP) CARATTERIZZATO DA UN RAPPORTO RAZIONALE TRA LE LE FREQUENZE D`INGRESSO E DI USCITA.
摘要
申请公布号
IT1252241(B)
申请公布日期
1995.06.05
申请号
IT1991MI03303
申请日期
1991.12.10
申请人
ALCATEL ITALIA S.P.A.
发明人
CUCCHI SILVIO;PONTE LUCA
分类号
H03L7/197;(IPC1-7):H03B
主分类号
H03L7/197
代理机构
代理人
主权项
地址
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