发明名称 SEMICONDUCTOR DEVICE
摘要 <p>PURPOSE:To provide a NAND cell type EEPROM in which the lowering of an effective channel length due to the oozing of a diffusion layer under a gate can be prevented and the coupling ratio of a memory cell can be increased. CONSTITUTION:This relates to an EEPROM in which a floating gate 15 and a control gate 17 are laminated for formation on a p-type Si substrate 10, in the surface of which an n-type well 11 is formed, and a plurality of memory cells which are electricallly rewritable with the giving and receiving of an electric charge between the floating gate and the substrate 10 are connected in series to constitute a NAND cell. Therefore, a conductive film 20 is formed on the control gate 17 and in the side surface of the control gate 17 and the floating gate 15 through an insulating film 19, and also the conductive film 20 is formed in a space between memory cells, thereby forming an inverting layer between the memory cells constituting an NAND cell by applying a voltage to the conductive layer 20.</p>
申请公布号 JPH07147406(A) 申请公布日期 1995.06.06
申请号 JP19940148098 申请日期 1994.06.29
申请人 TOSHIBA CORP 发明人 ENDO TETSUO
分类号 H01L29/78;H01L21/336;H01L21/8247;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):H01L29/78 主分类号 H01L29/78
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