| 摘要 |
<p>PURPOSE:To provide a parallel arithmetic unit which can perform the parallel arithmetic operations at a high speed by performing the switching between the SIMD and MIMD operations according to each problem and also can perform such a processing problem that includes both SIMD and MIMD operations at a high speed by eliminating the time loss caused by the switching of both operations. CONSTITUTION:The parallel arithmetic unit is provided with a two-dimensional memory array MAR which stores the data for arithmetic operations, a transfer network TN which transfers the data on the memory cells set on a word line which are read out of the array MAR in parallel to each other to the arithmetic circuit groups PE1 to PEn which carry out the arithmetic processings in parallel to each other based on the data received from the network TN, a signal line LS which transmits an instruction OP-s in an SIMD operation state, an instruction buffer BAF which stores the instructions OP-m in an MIMD operation state and transmits them in parallel to each other, and a switch group SW-OP which performs the switching between both SIMD and MIMD operations.</p> |
