| 摘要 |
PURPOSE: To produce VLSI for a necessary refresh cycle selective DRAM with a large capacity with a high economical efficiency by arraying DRAMs of a necessary capacity in a rectangle, arranging bonding pads corresponding to different power sources in the middle part, and operating the DRAMs in different modes. CONSTITUTION: Four pieces of 4MB DRAMs individually arrayed in 1st to 4th quadrants make a DRAM of 16MB occupying a small area. In the central part of this VLSI, forty-five bonding pads are divided into two and vertically arranged in a row, and one is selected for a first power source of 4K cycle, the other is selected for a second power source of 2K cycle, and the VLSI becomes a DRAM which works with the first and second options. Further, each peripheral circuit arrayed in the middle part is produced by a common process to different optional modes as far as possible. Thus, an ordinary 4K memory refresh cycle and 2K memory refresh cycle which is predicted to be customary in future becomes a VSLI for a freely selective and highly economical efficient 16MB DRAM.
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