| 摘要 |
PURPOSE:To accelerate search operation by controlling a data reproducing PLL circuit to enter no dead band controlled from neither a phase comparison result nor a frequency detection result. CONSTITUTION:By successively heightening an oscillation frequency of a voltage control oscillator VCO, the 11T-0.5T (T is period) of a phase clock PLCK is driven into so as to enter a polality inversion interval of an EFM (8 for 14 modulation) signals obtained from a data slice circuit. In such a case, the control heightening the oscillation frequency of the oscillator VCO is performed continuously even when entering a capture range by the control of only a phase comparison circuit. Then, when the 11T+0.5T of the phase clock PLCK enters the polarity inversion interval of the EFM signal, the control heightening the oscillation frequency of the oscillator VCO is stopped by a numeral B outputted from a maximum length register 27. Thus, the dead band from the phase comparison circuit and the frequency detection circuit 22 is eliminated by the data reproducing PLL circuit. |
