发明名称 METHOD AND CIRCUIT FOR PROCESSING CSI BIT
摘要 PURPOSE:To recognize truth/false of sent information automatically and immediately by detecting the reception of each specific number of a cell used to send information and providing an output of a signal representing invalid information when even one loss is detected. CONSTITUTION:This circuit is provided with individual reception detection sections 1, 3, 5, 7 each detecting the reception of each of received sequence numbers(SN) 1, 3, 5, 7, an odd number SN cell loss detection section 11 detecting the loss of any of odd number cell, and a 7-th cell loss detection section 12 detecting the loss of the cell SN7. Further, a timing pulse generating section 13, an RS-FF 10 of one RS flip-flop, CSI bit latch sections 21, 23, 25, 27 latching convergence sub-layer indication(CSI) of odd number cells and a D flip-flop 14 are provided. Then information is provided to a predetermined SN cell, a receiver side detects the reception of a CSI of each SN and a signal representing the loss is outputted when the loss of at least one cell is detected.
申请公布号 JPH07143132(A) 申请公布日期 1995.06.02
申请号 JP19930161096 申请日期 1993.06.30
申请人 NEC CORP;NIPPON TELEGR & TELEPH CORP <NTT> 发明人 MURAKAMI KOU;UEMATSU HITOSHI;UEDA HIROMI
分类号 H04L12/28;(IPC1-7):H04L12/28 主分类号 H04L12/28
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