| 摘要 |
PURPOSE:To provide a digital multiplying circuit capable of reducing the number of bits in an output in respect to a digital multiplying circuit for executing the multiplication of two-input digital signals expressed by 2's complement. CONSTITUTION:A multiplier 1 multiplies a 1st m-bit digital input signal to be a binary number expressed by a 2's complement inputted from an input terminal 2 and a 2nd n-bit digital input signal to be a binary number expressed by a 2's complement inputted from an input terminal 3 and outputs a multiplied result consisting of (n+m) bits. When the MSB of the multiplied result is the same as 2 bits of two SBs, an exclusive OR logic unit 6 selects (n+m-1) bits excluding the MSB of the multiplied result by a switch 7, and when the 2-bit value is different from the MSB, selects a set value consisting of (n+m-1) indicating a value obtained by subtracting '1' from the normal multiplied result. |
