发明名称 SYNCHRONIZING ADDER
摘要 <p>PURPOSE:To reduce the leakage of higher harmonic components into an envelope and to perform an accurate synchronizing addition by executing a waveform shaping to every other sub-carrier, squaring the result and eliminating the high harmonic components from this sum. CONSTITUTION:The synchronizing component I signals 13 and 15 and the orthogonal component Q signals 14 and 16 subjected to frequency conversion in frequency converters 35 and 36 are inputted to synthetic type waveform shaping filters 1 to 4 having a characteristic performing the waveform shaping to every other sub-carrier. The I signals 17 and 19 and Q signals 18 and 20 subjected to waveform shaping are squared in respective square circuits 5 to 8 and are added in an adder 9. The output of the adder 9 has high harmonic components four times as many as envelope components in addition to the envelope components because of a square operation in the circuits 5 to 8. These high harmonic components are eliminated by a low-pass filter 10 and only the envelope components are inputted to an adder 82. Thus, the leakage of the high harmonic components generated due to a square operation into the envelope is reduced and an accurate synchronizing addition can be performed.</p>
申请公布号 JPH07143087(A) 申请公布日期 1995.06.02
申请号 JP19930308582 申请日期 1993.11.16
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HIRAMATSU KATSUHIKO;IGAI KAZUNORI;ISHIKAWA KIMIHIKO
分类号 H04J1/00;H04L7/00;H04L7/02;H04L27/26;(IPC1-7):H04J1/00 主分类号 H04J1/00
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