Speicherwarteschlange für eine festgekoppelte Mehrprozessorenkonfiguration mit einem zweistufigen Cache-Pufferspeicher.,申请号DE19896022326-传众专利搜索

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发明名称	Speicherwarteschlange für eine festgekoppelte Mehrprozessorenkonfiguration mit einem zweistufigen Cache-Pufferspeicher.
摘要
申请公布号	DE68922326(D1)	申请公布日期	1995.06.01
申请号	DE19896022326	申请日期	1989.01.17
申请人	INTERNATIONAL BUSINESS MACHINES CORP., ARMONK, N.Y., US	发明人	GREGOR, STEPHEN LEE, ENDICOTT, NY 13760, US
分类号	G06F15/16;G06F12/08;(IPC1-7):G06F12/08	主分类号	G06F15/16
代理机构		代理人
主权项
地址

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