APPARATUS AND METHOD FOR ELIMINATING MAPPING JITTER

摘要

A desynchronizer (10) for eliminating output mapping jitter includes a demapper circuit (12) for reading asynchronous data and clock rate of an embedded signal within a synchronous channel (14). The payload data is buffered in an elastic store circuit (ESC) (17). The demapper circuit (12) outputs bit stuff and pointer justification timing adjustments (PJTAs) to an overhead gapfill circuit (OHGC) (19) and a pointer justification leaky accumulator circuit (PJLAC) (20). The OHGC (19) calculates overhead gaps within the payload data to generate a gapfill value (34). The PJLAC (20) determines the bit stuffs and pointer justifications in the payload data to produce an accumulated value (36). The gapfill and accumulated values (34, 36) are combined with an elastic fill value (EFV) (18) from the ESC (17) to eliminate instantaneous variations and reduce the effects of bit stuffing and PJTAs in the EFV (18). An adjusted fill value goes to a clock recovery PLL circuit (CRPLL) (29). The CRPLL (29) generates a clock for transmitting the data from the ESC (17).