The transistor arrangement includes an insulating film, a gate (20) and a source/drain (24) which are all arranged on a semiconductor substrate (11). The gate overlaps the source/drain at its edges. The source/drain are arranged below the gate. In one embodiment the gate is arranged so that it is spaced from the source/drain at its edges by a conducting film spacing part which is in contact with the source/drain. The conducting film spacing part is insulated from the semiconductor substrate and has a conducting film on one of its side walls.
