| 摘要 |
The circuit for compensating the phase difference generated when dividing the high frequency in parallel includes a synchronizing part(1) delaying the synchronous signal to provide the reference signal(V1); a comparator(2) combining the inverse(V2) and delay(V3) signals of the reference signal logically and providing the comparing signal at the next one dividing clock after falling edge of the reference signal; and a compensator(3) combining the output(V4) of the comparator and the previous dividing clock of the present one(V0), and delaying the combined output(V5) to provide the present dividing clock(V0) which phase difference is compensated.
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