发明名称 A data transfer circuit and a recording apparatus and method.
摘要 <p>A data transfer circuit or a recording apparatus includes an address setting unit for setting a start address for a buffer memory, an offset setting unit for setting an offset for the buffer memory, and an address creating unit for creating a predetermined number of consecutive transfer addresses to be supplied for the buffer memory using a reference address. The circuit also includes an arithmetic logic unit that, after the address creating unit has created transfer addresses using the start address as a reference address, calculates a new reference address in accordance with the offset relative to the start address so as to provide the new reference address to the address creating unit. <IMAGE></p>
申请公布号 EP0655706(A1) 申请公布日期 1995.05.31
申请号 EP19940308546 申请日期 1994.11.18
申请人 CANON KABUSHIKI KAISHA 发明人 NAKATA, KAZUHIRO, CANON KABUSHIKI KAISHA;HIRASAWA, SHINICHI, CANON KABUSHIKI KAISHA;YAMAMOTO, TADASHI, CANON KABUSHIKI KAISHA;INUI, TOSHIHARU, CANON KABUSHIKI KAISHA;NAKAJIMA, KAZUHIRO, CANON KABUSHIKI KAISHA
分类号 G06F3/12;G06K15/10;(IPC1-7):G06K15/00 主分类号 G06F3/12
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