发明名称 Method and apparatus for controlling instruction in pipeline processor.
摘要 <p>A pipeline processor for processing instruction fetch prior to execution of the instruction based on the content of branch history for storing history of the result of execution of branch instructions includes an address generating section 12, branch history retrieving section 14, prefetch address holding section 16 and instruction fetch section 18. The branch history retrieving section 14 determines whether each of addresses sequentially generated from the address generating section 12 hits the branch history or not. When an instruction stored in the address hits the branch history, the branch history retrieving section 14 supplies the content of the branch history to the prefetch address holding section 16. When the branch history retrieving section 14 is hit, the prefetch address holding section 16 holds the branching-destination address of the branch instruction until the instruction is fetched by the instruction fetch section. If an instruction fetched in a preceding cycle hits the branch history, the instruction fetch section 18 fetches an instruction of an address held in the prefetch address holding section 16, and if the instruction fetched in a preceding cycle does not hit the branch history, the instruction fetch section 18 fetches an instruction of an address generated from the address generating section 12. &lt;IMAGE&gt;</p>
申请公布号 EP0655679(A2) 申请公布日期 1995.05.31
申请号 EP19940306879 申请日期 1994.09.20
申请人 FUJITSU LIMITED 发明人 INOUE, AIICHIRO, C/O FUJITSU LIMITED
分类号 G06F9/38;(IPC1-7):G06F9/38 主分类号 G06F9/38
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