发明名称 |
Coprocessor interface supporting I/O or memory mapped communications |
摘要 |
A coprocessor 18 comprises a bus controller 24 which further comprises a primary bus controller 28 and a secondary bus controller 30 that drive a floating point processor core 26. The primary bus controller 28 comprises a memory mapped bus interface 32 for processing memory mapped format instructions and an I/O bus interface 34 for processing conventional I/O format instructions. The primary bus controller 28 remains essentially transparent for execution of I/O format instructions and translates memory mapped format instructions into sequential bus cycles compatible to an I/O bus interface for processing conventional I/O format instructions, and for execution by the floating point processor core.
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申请公布号 |
US5420989(A) |
申请公布日期 |
1995.05.30 |
申请号 |
US19910713812 |
申请日期 |
1991.06.12 |
申请人 |
CYRIX CORPORATION |
发明人 |
MAHER, III, ROBERT D.;EITRHEIM, JOHN;DUNLAP, FRED;BRIGHTMAN, THOMAS B. |
分类号 |
G06F9/38;(IPC1-7):G06F9/30;G06F15/16 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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