Data processor for processing instruction after conditional branch instruction at high speed

摘要

A data processor includes a first circuit for decoding a sequence of instruction including a conditional branch instruction in such a manner that said conditional branch instruction is decoded and an instruction fetched after said conditional branch instruction is decoded before a branch condition for said conditional branch instruction has not decided. Said first circuit generates an operand address for the decoded instruction and a first signal indicating that said operand address is one generated before a branch condition is decided. A second circuit generates, after decision of said branch condition, a second signal indicating whether or not an instruction decoded after said conditional branch instruction is executed. The bus interface circuit performs replacement of a content of an associative memory. A control circuit receives the first and second signals and operates to hold replacement of a content of the associative memory.