VERTICAL DOUBLE DIFFUSION TYPE POWER MOSFET AND ITS MAKING METHOD

摘要

This method minimizes the unit cell area, simplifies the fabrication process by forming n+-type source region by using an insulating layer which is doped with n-type impurity. The method comprises the steps of: supplying n+-type silicon substrate (10); growing n--type epitaxial layer (11) on the substrate; forming a thin gate oxide layer on the top of the epitaxial layer; depositing polycrystal silicon layer on the thin gate oxide layer; etching the some parts of the polycrystsal silicon by using a mask; forming a gate electrode (13); depositing a silicon oxide layer (14) which is doped with n-type impurity; etching the some parts of the silicon oxide layer with a mask; forming n+-type junction (15) by the diffusion of the n-type impurity from contact hole (14') into the n--type epitaxial layer; depositing metal in some thickness; and forming a source electrode (16)