发明名称 Clock apparatus for a compressed video signal.
摘要 Apparatus for developing synchronization of an intermediate layer of signal such as the transport or multiplex layer of a multi-layered compressed video signal, includes at the encoding end of the system a modulo K counter (23) which is clocked responsive to a system clock (22), and the count valued is embedded (13) in the signal at the transport layer according to a predetermined schedule. At the receiving end of the system a similar counter is responsive to a controlled receiver clock signal (26) and the count value of this counter is sampled (18) at the arrival of the count values embedded in the transport layer. The differences of successive sampled count values of the receiver counter are compared with the differences of corresponding successive values of the embedded count values in the transport layer to provide a signal to control (27) the receiver clock signal. <IMAGE>
申请公布号 EP0624982(A3) 申请公布日期 1995.05.24
申请号 EP19940106946 申请日期 1994.05.04
申请人 THOMSON CONSUMER ELECTRONICS 发明人 DEISS MICHAEL SCOTT
分类号 H04B1/66;G06T9/00;H03L7/085;H03L7/181;H04J3/00;H04L7/00;H04L7/033;H04L12/70;H04L13/08;H04N7/08;H04N7/081;H04N7/24;H04N7/62;H04N11/04;H04N19/00;H04N19/89;H04N21/236;H04N21/43;H04N21/434 主分类号 H04B1/66
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