| 摘要 |
The circuit comprises a first and a second voltage-controlled oscillator (4, 14) having identical characteristics. The first oscillator (4) is incorporated into a frequency synthesis loop (3) in such a way as to oscillate, in response to a first control voltage (V1), at a frequency equal to a reference frequency multiplied by a number N. The second voltage-controlled oscillator (14) is incorporated into a phase tracking loop (13) which, when it is activated, locks its oscillation phase relative to that of the received data signal (SD). The second oscillator (14) delivers the recovered clock signal (CLK2). A comparator (20) determines whether the frequency of the second oscillator (14), divided by N, satisfies the condition of not deviating from the reference frequency by more than a predetermined limit value. The phase tracking loop (13) is activated only when the said condition is satisfied, and the first control voltage (V1) is fed to the control input of the second oscillator when the said condition is not satisfied. <IMAGE> |
