| 摘要 |
PCT No. PCT/DE93/00542 Sec. 371 Date Feb. 10, 1995 Sec. 102(e) Date Feb. 10, 1995 PCT Filed Jun. 23, 1993 PCT Pub. No. WO94/03898 PCT Pub. Date Feb. 17, 1994In a DRAM cell arrangement, two memory cells which include an MOS transistor and a memory element are constructed in each case as a transistor pair (10) whose source areas are connected to one another and to a bitline (11). The MOS transistors have a linear arrangement of the drain area, the gate electrode and the source area which is aligned in the direction of the bitlines (11) and which is arranged essentially below a bitline (11). Adjoining the drain area in each case is a terminal area (13) which is arranged to the side of associated bitlines (11) and via which a cell contact to the memory element is formed. The cell arrangement is particularly suitable for buried-bitline-stacked-capacitor (BBSTC) DRAM cells. |
