HIGH-INTEGRATION-DENSITY STACKED GATE EPROM SPLIT CELL PROVIDED WITH BIT-LINE REACH-THROUGH AND WITH INTERRUPT IMMUNITY

摘要

PURPOSE: To provide a method for manufacturing a separation gate EPROM cell with a stacking etching technology with which interruption of bit lines and penetration between bit lines are prevented. CONSTITUTION: A silicon dioxide layer 52 is formed on a P-silicon substrate. A polysilicon layer 56 is formed on the layer. An oxide/nitride/oxide(ONO) layer 54 is grown. The layers 56 and 54 are etched to trace floating gates 56 one end of which is used for self-alignment implantation of buried N+ bit lines 60 and 62. A discriminating oxide layer 64 is grown on the substrate between adjacent floating gates. A second polysilicon layer is formed and etched for tracing controlling lines 70 which extend orthogonally to the floating gates in a conventional separation gate EPROM cell structure.