发明名称 Fast communication link bit error rate estimator
摘要 A system and method is provided for estimating the bit error rate of a data signal which has been reconstructed from a received data signal. The system comprises (i) logic for determining timing degradation and amplitude degradation of the received data signal; (ii) an actual bit error rate calculator for calculating the actual bit error rate of the reconstructed data signal; (iii) an instantaneous bit error rate calculator for estimating a bit error rate of the reconstructed signal using the timing degradation and the amplitude degradation; (iv) a first integrator for integrating the estimated bit error rate; (v) a comparator for comparing the integrated estimated bit error rate with the actual bit error rate and outputting an error signal which modifies the estimated bit error rate; and (vi) a second integrator for integrating the estimated bit error rate. The time constant associated with the second integrator is shorter than the time constant associated with the first integrator.
申请公布号 US5418789(A) 申请公布日期 1995.05.23
申请号 US19920960971 申请日期 1992.10.14
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 GERSBACH, JOHN E.;NOVOF, ILYA I.;LEE, JOSEPH K.
分类号 H04L1/20;(IPC1-7):G06F11/00;H04B17/00 主分类号 H04L1/20
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