| 摘要 |
The generation of a test for detecting faults in a circuit (10) can be speeded up by first selecting a successive one of a first set of faults for targeting and thereafter determining the effort required to detect a predetermined number of the first set of faults. Each of the remaining faults is then successively targeted, with the amount of effort spent to detect each of the remaining faults being adjusted in accordance with the amount of effort spent detecting the previously targeted fault. In each test cycle, faults that are untestable, or too difficult to detect during that cycle, are eliminated from consideration to improve the efficiency and speed of the test generation process.
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