| 摘要 |
An apparatus and method enables elements of a phase locked loop (PLL) (300). The PLL (300) includes a plurality of elements (202, 203, 204, 205). Each element produces an output signal (207, 208, 209, 116 or 117). Each element has a response time t3-t2 defined by the difference in time between a first time t2 at which the element is enabled and a second time t3, occurring after the first time t2, at which the output signal of the element reaches a steady state condition. A voltage controlled oscillator (204) of the plurality of elements, having a first response time t3-t2 is enabled at the first time t2 responsive to a first control signal (302). A loop divider (205) of the plurality of elements, having a second response time less than the first response time t3-t2, is enabled responsive to the first response time t3-t2 and a second control signal (303). The present invention advantageously provides fast lock time for the PLL (300).
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