发明名称 DUPLEX PACKET BUS SELECTING CIRCUIT OF PACKET PROCESSING DEVICE
摘要 When data transmission between packet processing units or between a control processor and packet processing unit, the selection circuit selects multiple packet bus which enhances reliability of data transmission. Selection circuit comprises interrupt processing unit to generate operate/wait selection control interrupt to packet processing unit; state change detection unit to generating operate/wait state change interrupt by comparing old state and current state of operate/wait signal.
申请公布号 KR950005148(B1) 申请公布日期 1995.05.18
申请号 KR19910023139 申请日期 1991.12.17
申请人 KOREA ELECTRONICS & TELECOMMUNICATIONS RESEARCH INSTITUTE 发明人 LEE, HYONG - HO;PARK, JU - YOL;HONG, HYON - HA;HAN, CHI - MUN
分类号 H04L12/40;(IPC1-7):H04L12/56 主分类号 H04L12/40
代理机构 代理人
主权项
地址