发明名称 Wafer flow architecture for production wafer processing.
摘要 <p>A method for controlling the flow of semiconductor wafers within a semiconductor wafer processing facility. This method includes a wafer storage and preparation area (10) and a wafer metrology and etch area (12), both of which are monitored and/or controlled by a master controller (14). The wafer storage and preparation area (10) is typically kept at a class 10 clean room level and is comprised of a wafer storage area (16) and a wafer preparation area (18). The wafer metrology and etch area (12) is typically kept at a class 1000 clean room level and is comprised of an I/O cassette module (22), a wafer pre-aligner (24), a wafer router (26), a wafer metrology instrument (28), and a wafer etching instrument (30). The semiconductor wafers are transported, either manually or automatically, between the wafer storage area (16) and the wafer preparation area (18), as well as between the wafer storage and preparation area (10) and the wafer metrology and etch area (12), within wafer storage cassettes (20). The semiconductor wafers are individually transported between the I/O cassette module (22), the wafer pre-aligner (24), the wafer metrology instrument (28), and the wafer etching instrument (30) by the wafer router (26). &lt;IMAGE&gt;</p>
申请公布号 EP0653780(A1) 申请公布日期 1995.05.17
申请号 EP19940308114 申请日期 1994.11.03
申请人 HUGHES AIRCRAFT COMPANY 发明人 POULTNEY, SHERMAN K.;MUMOLA, PETER B.;MCHUGH, THOMAS J.;PRUSAK, JOSEPH P.;GARDOPEE, GEORGE J.
分类号 H01L21/302;H01L21/00;H01L21/02;H01L21/306;H01L21/677;(IPC1-7):H01L21/00 主分类号 H01L21/302
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