| 摘要 |
The variable and controllable delay circuit having a signal input (1), a control input (3) for a control signal, a signal output (2) for delivering a signal which is time delayed with respect to the input signal (SE), and delay means including a logic circuit (4) connected between the signal input and the signal output, as well as a load circuit including a capacitive load (10) connected at the output (9) of the logic circuit (4); the impedance of the load circuit is alterable under the action of the control signal in order to vary the said delay. The capacitive load (10) is variable under the action of the control signal (b3, b2, b1) to take different capacitive values.
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