| 摘要 |
An analog-to-digital converter having at least one stage, each stage comprising an array of capacitors, one or more comparators, an operational amplifier, and switches. Each stage operates in two phases, the sampling phase and the amplifying phase. During the sampling phase, the input voltage is sampled on the capacitor array. During the amplifying phase, one plate of each capacitors is connected to the reference voltage, ground, or the output of the operational amplifier to produce a residue voltage. Each of the array is sequentially connected to the output of the operational amplifier as the input voltage increases. The resulting residue drop for each digital code increase is precisely equal to the full-scale voltage. Combined with over-range and digital error-correction, the resulting A/D converter exhibits excellent differential linearity.
|
