| 摘要 |
In a circuit design support system, a logic minimizing unit receives data indicating a functional specification of a desired circuit and minimizes logical sequences of the desired circuit. A cell assignment unit assigns cells to each of minimized logical sequences determined by the logic minimizing unit and generates data on a circuit configuration of the desired circuit. The cells are logic units. A load/timing check unit receives the data on the circuit configuration and simultaneously executes a load check and a timing check. The load check determines whether or not the circuit configuration has a load driving ability within a tolerable load driving ability. The timing check determines whether or not the circuit configuration has a delay time of a signal within a tolerable delay time. A load adjustment unit executes a load adjustment of the circuit configuration on the basis of a result of the load check so that the load driving ability of the circuit configuration falls within the tolerable driving ability. A timing adjustment unit executes a timing adjustment of the circuit configuration on the basis of a result of the timing check so that the delay time of the circuit configuration falls within the tolerable delay time.
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